Proposals for analog noise generation using chaotic circuits preceded the works on chaotic Random Number Generators (“RNG's”). White noise generation using the logistic map was analyzed in “Generation of Noise by Electronic Iteration of the Logistic Map” (G. C. McGonigal and M. I. Elmasry, IEEE Trans. Circ. Syst., vol. CAS-34, pp. 981-983, 1987), while for the same purpose a 1D piecewise linear map was used in “Switched-capacitor broadband noise generator for CMOS VLSI” (Rodriguez-Vasquez, M. Delgado, S. Espejo, and J. L. Huertas, Electronics letters, vol. 27, no. 21, pp. 1913-1915, October 1991. In “A chaotic switched-capacitor circuit for 1/f noise generation” (M. Delgado-Restituto, A. Rodriguez-Vasquez, S. Espejo, and J. L. Huertas, IEEE Trans. Circ. and Syst.-I, vol. 9, no. 4, pp. 325-328, April 1992) hopping transitions of a 1D piecewise linear chaotic map are used for 1/f noise generation. Some of these papers also mention RNG as possible application of their circuits.
Still the era of chaotic RNGs begins with the works of Bernstein and Lieberman (G. M. Bernstein and M. A. Lieberman, “Secure random number generation using chaotic circuits”, IEEE Trans. Circ. Syst., vol. 37, pp. 1157-1164, 1990), and Espejo-Meana et al. (S. Espejo-Meana, A. Rodriguez-Vazquez, J. L. Huertas, and J. M. Quintana, “Application of chaotic switched-capacitor circuits for random-number generation”, European conference on circuit theory and design 1989, pp. 440-444, 1989). In these two papers and in those following them, chaotic circuits serve as physical sources of randomness. Tent map implemented via switched-capacitor circuits and a first-order nonuniformly sampling digital phase-locked loop is used to produce a binary random sequence through a binary quantization of a chaotic signal.
Failures or drops in performances may silently occur in classical RNGs, and periodic check-ups (via the black magic of complicated statistical tests) and tune-ups are necessary to maintain the performances. Using chaotic circuits, a possible solution for this problem can be achieved by tuning the nominal parameter values to lie in the middle of the region of parameter values that provide a chaotic behavior. However, in today IC technology the process variations, power supply fluctuations, temperature changes, clock feed-through and other influences are likely to cause the nonlinear circuit to leave the parameter region of chaotic behavior.
The availability of high quality random number generators is essential to the effectiveness of a cryptographic system. With the advent of very large-scale integrated circuits (VLSI), and the embodiment of cryptographic systems in VLSI, it is important that component random number generators be compatible with VLSI circuit processing. Various pseudo-random number generators have been developed in the prior art, however they are all subject to attack by an eavesdropper with the intention of circumventing the cryptographic system.
Turning now to FIG. 1A there is shown an exemplary single ended chaos circuit. The signal X[n] (140) enters the Linearized Sample and Hold (LSH) circuit portion (130), the output of the LSH is: B*X[n] (150)—wherein B is a predefined constant. The output of the LSH is then used as the input of a Non-Linear Discriminator (NLD), which is depicted in FIG. 1B as well.
The NLD extracts the SIGN of the entered signal, meaning, if the signal is equal or higher than a certain threshold, then SIGN(X) is “+” otherwise it is “−”, wherein “+” and “−” are used as unary operators. The NLD outputs equals: −A*SIGN(X[n]) (160), wherein “A” is a predefined constant.
The single ended chaos architecture may be characterized by a one-loop feed back (110) which returns the output of the Non-Linear Discriminator (NLD) to the input of the Linearized Sample and Hold (LSH).
The Finite Difference Equation (FDE), which is employed by this circuit, is very sensitive to the value of equation coefficients and equation non-idealities. Circuits implementing chaotic FDE must be very accurate and bounded with narrower margins than those needed by most analog applications.
FDE non-idealities and small variations in the coefficients may originate from variation in operation conditions and process. Previous single ended chaos-based IC implementations were tunes to function under nominal conditions, but their performance degraded a corner condition.
The problem of degraded performance at corner condition may aggravate in today's analog IC's that work under strict voltage budget, and have a reduced overdrive voltage.
Therefore because of the problems described above, there exists a need in the field of IC design and fabrication for an improved pseudo-random numbers generator using chaos circuits.